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| CY62158E MoBL(R) 8-Mbit (1M x 8) Static RAM Features Very high speed: 45 ns Wide voltage range: 4.5V - 5.5V Ultra low active power Typical active current:1.8 mA @ f = 1 MHz Typical active current: 18 mA @ f = fmax Ultra low standby power Typical standby current: 2 A Maximum standby current: 8 A Easy memory expansion with CE1, CE2 and OE features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb-free 44-Pin TSOP II package is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Placing the device into standby mode reduces power consumption significantly when deselected (CE1 HIGH or CE2 LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and OE LOW while forcing the WE HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or a write operation is in progress (CE1 LOW and CE2 HIGH and WE LOW). See the Truth Table on page 8 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Functional Description The CY62158E MoBL(R) is a high performance CMOS static RAM organized as 1024K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This Logic Block Diagram CE1 CE2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 WE OE DATA IN DRIVERS ROW DECODER IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6 1024K x 8 ARRAY COLUMN DECODER POWER DOWN IO7 Cypress Semiconductor Corporation Document #: 38-05684 Rev. *D * 198 Champion Court A15 A16 A17 A13 A14 A18 A19 * San Jose, CA 95134-1709 * 408-943-2600 Revised June 16, 2008 [+] Feedback CY62158E MoBL(R) Pin Configuration Figure 1. 44-Pin TSOP II (Top View) [1] A4 A3 A2 A1 A0 CE1 NC NC IO0 IO1 VCC VSS IO2 IO3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CE2 A8 NC NC IO7 IO6 VSS VCC IO5 IO4 NC NC A9 A10 A11 A12 A13 A14 Product Portfolio Power Dissipation Product VCC Range (V) Typ [2] 5.0 Speed (ns) Max 5.5 45 Typ [2] 1.8 Operating ICC (mA) f = 1 MHz Min CY62158ELL 4.5 Max 3 f = fmax Typ [2] 18 Max 25 Standby ISB2 (A) Typ [2] 2 Max 8 Notes 1. NC pins are not connected on the die. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C. Document #: 38-05684 Rev. *D Page 2 of 10 [+] Feedback CY62158E MoBL(R) Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage to Ground Potential -0.5V to VCC(max) + 0.5V DC Voltage Applied to Outputs in High-Z State [3, 4] ........................-0.5V to VCC(max) + 0.5V DC Input Voltage [3, 4] .....................-0.5V to VCC(max) + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Operating Range Device CY62158ELL Range Ambient Temperature VCC [5] Industrial -40C to +85C 4.5V - 5.5V Electrical Characteristics Over the Operating Range -45 Parameter VOH VOL VIH VIIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power down Current -- CMOS Inputs IOH = -1 mA IOL = 2.1 mA VCC = 4.5V to 5.5V VCC = 4.5V to 5.5V GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels 2.2 -0.5 -1 -1 18 1.8 2 Test Conditions Min 2.4 0.4 VCC + 0.5V 0.8 +1 +1 25 3 8 Typ [2] Max Unit V V V V A A mA mA A ISB1 CE1 > VCC- 0.2V, CE2 < 0.2V VIN > VCC - 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), f = 0 (OE, and WE), VCC = VCCmax CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = VCCmax ISB2 [6] Automatic CE Power-down Current -- CMOS Inputs 2 8 A Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP II 75.13 8.95 Unit C/W C/W Notes 3. VIL(min) = -2.0V for pulse durations less than 20 ns. 4. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 5. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization. 6. Only chip enables (CE1 and CE2), must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 38-05684 Rev. *D Page 3 of 10 [+] Feedback CY62158E MoBL(R) Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 3V GND 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V Parameters R1 R2 RTH VTH 1838 994 645 1.75 5.0V V Unit Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR [6] Description VCC for Data Retention Data Retention Current Conditions Min 2 Typ [2] Max Unit V A VCC = VDR CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Figure 3. Data Retention Waveform 8 tCDR [7] tR [8] Chip Deselect to Data Retention Time Operation Recovery Time ns ns VCC CE1 VCC(min) tCDR DATA RETENTION MODE VDR > 2.0 V VCC(min) tR or CE2 Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document #: 38-05684 Rev. *D Page 4 of 10 [+] Feedback CY62158E MoBL(R) Switching Characteristics Over the Operating Range [9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [12] Description 45 ns Min Max Unit Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z [10] OE HIGH to High Z [10, 11] [10] 45 45 10 45 22 5 18 10 18 0 45 45 35 35 0 0 35 25 0 18 10 [10, 11] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 LOW and CE2 HIGH to Low Z CE1 HIGH or CE2 LOW to High Z CE1 LOW and CE2 HIGH to Power Up CE1 HIGH or CE2 LOW to Power Down Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z [10, 11] WE HIGH to Low Z [10] Notes 9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in "AC Test Loads and Waveforms" on page 4. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05684 Rev. *D Page 5 of 10 [+] Feedback CY62158E MoBL(R) Switching Waveforms Figure 4 shows address transition controlled read cycle waveforms.[13, 14] Figure 4. Read Cycle No. 1 tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 5 shows OE controlled read cycle waveforms.[14, 15] Figure 5. Read Cycle No. 2 ADDRESS tRC CE1 CE2 tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Notes 13. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 14. WE is HIGH for read cycle. 15. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document #: 38-05684 Rev. *D Page 6 of 10 [+] Feedback CY62158E MoBL(R) Switching Waveforms (continued) Figure 6 shows WE controlled write cycle waveforms.[12, 16, 17] Figure 6. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA IO NOTE 18 tHZOE VALID DATA tHD Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[12, 16, 17] Figure 7. Write Cycle No. 2 tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA OE tSD DATA IO VALID DATA tHD Notes 16. Data IO is high impedance if OE = VIH. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals. Document #: 38-05684 Rev. *D Page 7 of 10 [+] Feedback CY62158E MoBL(R) Switching Waveforms (continued) Figure 8 shows WE controlled, OE LOW write cycle waveforms.[17] Figure 8. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATA IO NOTE 18 tHZWE VALID DATA tLZWE tHD tPWE tHA Truth Table CE1 H X L L L X L H H H CE2 X X H H L WE X X L H X OE Inputs/Outputs High Z High Z Data Out High Z Data in Mode Deselect/Power Down Deselect/Power Down Read Output Disabled Write Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 45 Ordering Code CY62158ELL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85087 44-Pin TSOP II (Pb-free) Document #: 38-05684 Rev. *D Page 8 of 10 [+] Feedback CY62158E MoBL(R) Package Diagrams Figure 9. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 38-05684 Rev. *D Page 9 of 10 [+] Feedback CY62158E MoBL(R) Document History Page Document Title: CY62158E MoBL(R) 8-Mbit (1M x 8) Static RAM Document Number: 38-05684 REV. ** *A ECN NO. 270350 291271 Issue Date See ECN See ECN Orig. of Change PCI SYT Description of Change New Data Sheet Converted from Advance Information to Preliminary Changed input pulse level from VCC to 3V in the AC Test Loads and Waveforms Modified footnote #9 to include timing reference level of 1.5V and input pulse level of 3V *B 1462592 See ECN VKN/AESA Converted from preliminary to final Removed 35 ns speed bin Removed "L" parts Removed 48-Ball VFBGA package Changed ICC(max) spec from 2.3 mA to 3 mA at f=1 MHz Changed ICC(typ) spec from 16 mA to 18 mA at f=fMAX Changed ICC(max) spec from 28 mA to 25 mA at f=fMAX Changed ISB1(typ) and ISB2(typ) spec from 0.9 A to 2 A Changed ISB1(max) and ISB2(max) spec from 4.5 A to 8 A Changed ICCDR(max) spec from 4.5 A to 8 A Changed tLZOE spec from 3 ns to 5 ns Changed tLZCE spec from 6 ns to 10 ns Changed tHZCE spec from 22 ns to 18 ns Changed tPWE spec from 30 ns to 35 ns Changed tSD spec from 22 ns to 25 ns Changed tLZWE spec from 6 ns to 10 ns Added footnote# 6 related to ISB2 and ICCDR Updated Ordering information table VKN/PYRS Corrected typo in the Ordering Information table PYRS Corrected ECN number *C *D 2428708 2516494 See ECN See ECN (c) Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05684 Rev. *D Revised June 16, 2008 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback |
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